The University of Aizu, Aizu-Wakamatsu City, Japan
September 20 - 22, 2012
Keynote Speakers
Travel Information
Sponsored by the University of Aizu and the
Technical Committees on Microprocessors and
Microcomputers  of the IEEE Computer Society. In
cooperation with the IEICE CPSY Society and the
IEEE Sendai Section.
Chief Professional, Renesas Electronics Corp., Japan

Trend of Multi-/Many-core for Embedded Systems
A multi-/many-core is one of the most promising approaches to realize high-efficiency, which is
the key factor to achieve high-performance under some fixed power and cost budgets. A cloud
system enables thin clients in many cases relying on high-performance of severs remotely
connected by network; however, it is still desirable to accomplish a real-time or dependable
operation locally by an embedded system. This is because some critical operation does not allow
slow or unpredictable response caused by network delay or disconnection. Such a disadvantage
of network should be concealed from a user. Therefore, embedded systems will employ multi-
/many-core architecture more and more to realize various cool functionalities with/without network.
A heterogeneous multi-core chip, RP-X integrates eight SH-X4 CPU cores, four flexible engine
(FE) cores, two matrix processor (MX) cores, and a video processing unit (VPU). The SH-X4 cores
run at 648MHz and achieve totally 13.7 Dhrystone GIPS and 36.3 peak GFLOPS. Overall, the RP-X
achieves 114.7GOPS with 3.07W, and the power-performance ratio is as high as 37.3 GOPS/W.

Biography: Fumio Arakawa is a chief professional in the System Core Development Division of
Renesas Electronics. His research interests include architecture and micro-architecture of low-
power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from
the University of Tokyo. He’s a program committee co-chair of the Cool Chips conference series,
a guest editor of COOL Chips Special Section/Issue of IEEE Micro, a program committee member
of the VLSI Circuits Symposium, and the chairman of Microprocessor Technical Committee and
Multi-/Many-core Application Research Committee of Japan Electronics and Information
Technology Industries Association. He’s a member of IEEE and IEICE.
Professor, University of Bologna, Italy

Scalable Many-core Acceleration for Image Understanding - is CPU+GPU the answer?
Image understanding is becoming the next "killer app" for mobile and embedded platforms and
devices. Visual search, face and gesture recognition, SLAM, 3D reconstruction are
computationally intensive and complex algorithms which will have to run in real-time with a very
modest power budget in next-generation smart phones, tablets, TVs...  
The hunt for  the best computational engine for image understanding is now open. Some serious
contenders are already emerging, high-frequency SMP-style embedded CPUs and  GP-GPUs
being the main ones.  In this talk I would discuss the pros and cons of these architectures in
running image understanding applications, and I will give my view
and experience in designing an alternative scalable computational fabric to hit the sweet spot in
terms of GOPS/mm2/W while preserving a standard-based software API for ecosystem build-up
and application integration.

Biography: Lca Benini is Full Professor at the Department of Electrical Engineering and Computer
Science (DEIS)of the University of Bologna, Italy. He also holds a visiting faculty position at the
Ecole Polytechnique Federale de Lausanne (EPFL) and he is currently serving as Chief Architect
for the Platform 2012 project in STmicroelectronics, Grenoble. He received a Ph.D. degree in
electrical engineering from Stanford University in 1997. Dr. Benini's research interests are in
energy-efficient system design and Multi-Core SoC design. He is also active in the area of
energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence
applications. He has published more than 500 papers in peer-reviewed international journals and
conferences, four books and several book chapters. He has been general chair and program
chair of the Design Automation and Test in Europe Conference. He has been a member of the
technical program committee and organizing committee of several conferences, including the
Design Automation Conference, International Symposium on Low Power Design, the Symposium
on HardwareSoftware Codesign. He has been Associate Editor of several international journals,
including the the IEEE  Transactions on Computer Aided Design of Circuits and Systems and the
ACM Transactions on Embedded  Computing Systems. He is a Fellow of the IEEE, a member of
the Academia Europaea, and a member of the  steering board of the ARTEMISIA European
Association on Advanced Research & Technology for Embedded  Intelligence and Systems.
Dr. Sofiène TAHAR
Professor, Concordia University, Montreal, Canada

System-on-Chip Design Verification: Challenges and State-of-the-art
We address an important area of System-on-Chip R&D activity, namely "Design Verification".
Verification today is known to cost about 70% of industrial electronics design projects, in terms of
human, computer and budget. Many product delays are caused by verification taking longer than
expected, and despite multiple efforts, products are delivered with uncaught bugs. We present the
different kinds of verifications used today in an industrial design flow, namely design,
implementation and fabrication verification. We then focus more on design verification from high
level specification to gate level implementation. Several technologies will be displayed and
compared, drawing a picture to still open problems and possible research issues. Among them
"formal verification" is one of the most active areas that is carried out since recently and which
make use of computerized mathematical reasoning to verify system properties. Example
applications of this technology used in industry scale projects will be presented and discussed.

Biography: Sofiene Tahar received in 1990 the Diploma degree in computer engineering from the
University of Darmstadt, Germany, and in 1994 the Ph.D. degree with "Distinction" in computer
science from the University of Karlsruhe, Germany. Currently he is Professor in the Department of
Electrical and Computer Engineering at Concordia University, Montreal, Quebec, Canada, where
he is holding a Senior Research Chair in Formal Verification of System-on-Chip. Prof. Tahar is
founder and director of the Hardware Verification Group at Concordia University, which focuses on
developing verification technologies in the fields of microelectronics, telecommunications,
security, aviation, etc. He has received several awards and distinctions, including in 2010 a
National Discovery Award, given
to Canada's top 100 researchers in engineering and natural sciences. Prof. Tahar is senior
member of IEEE and member of the Order of Engineers of Quebec, ACM, IEEE Computer and
IEEE Communications Societies.
Dr. Hideharu AMANO
Professor, Keio University, Japan

An NoC Architecture for Inductive Coupling Wireless Interconnect
The initial cost of LSI for design and mask is growing in advanced technologies, and developing
various types of SoC (System-on-a-Chip)s for required application has become difficult.  SiP
(System in Package) or 3-dimensional implementation techniques can address the problem by
connecting multiple dies.Various scales and functions can be realized from various combination
of dies.
Especially, inductive coupling wireless 3-D connection is attractive because of its flexibility. An
NoC architecture which enables to replace and add dies is proposed. By using a simple ring
topology and bubble-flow control, dies can be connected and switched without deadlock. The
experience using a prototype chip Cube-0 is reported.

Biography: Hideharu Amano received the Ph.D degree from Keio University, Japan in 1986. He is
now a Professor
in the Department of Information and Computer Science, Keio University.  His research interests
include the area of
parallel architectures and reconfigurable computing.
President, TOPS Systems Corp., Japan

Cool System: A Scalable and Energy-Efficient 3D Heterogeneous Multi-Chip System with Cool
Interconnect, Cool Chip, and Cool Software
“Smart” Information Systems, such as next-generation Smart Phones, Tablets, Smart-TVs,  
Automotive safety systems, etc. drive evolution of SoC architecture to meet these system
requirements such as high performance with scalability and flexibility of functionality, with low-
power and low-cost in short time-to-market, that currently limited by SOCs integrating multiple
processor cores and a number of hardwired accelerator IPs. 3-D Multi-Chip stacking is a
promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”.
In this presentation, I introduce a vision and architecture of Cool System that consists of three
fundamental technologies, such as 1) Cool Chip, to make a high performance microprocessor
chip to be low-power enough to avoid heat issue, 2) Cool Software, to increase processor core
utilization with distributed processing software, and 3) Cool Interconnect, to enable low-power and
scalable 3D Multi-Chip stacking of heterogeneous LSIs. Cool System architecture takes an
approach to drastically reduce the operating clock frequency, but keep the high performance with
several hardware-software techniques and optimizations through architecture-and-algorithm co-
design. 1) Cool Chip architecture has features such as, a heterogeneous Multi-Core with stream
processing cores, distributed parallel processing with zero-overhead message passing
mechanisms, application domain specific heterogeneous Multi-Core configurations in Instruction
Set Architecture and , etc. 2) Cool Software is a distributed parallel processing software based on
Kahn Process Network Model with stream processing scheduling. 3) Cool Interconnect is a
common interface to enable scalable and heterogeneous Multi-Chips stacking with low-power
wide bandwidth communication.Example application domains, such as next generation DTV and
Video Mining, and their domain specific architectural solutions will be presented. In addition, the
architectural details and characteristics of Cool Interconnect test chip and Cool System test chips
will be presented.

Biography: Dr. Yukoh Matsumoto is the chief architect, and president and CEO of TOPS Systems
Corp. He led “Cool System : Ultra-Low-Power 3D stacked heterogeneous Multicore / Multichip”
project supported by NEDO and “Ultra-Android : Distributed Processing embedded software
platform” project supported by METI. Currently, he is working on “Low-Power Many-Core
Architecture and Compiler Technology” project supported by NEDO. In his 26 years of carrier, he
has architected and designed over 10 advanced microprocessors such as, Embedded Multicore
processors, x86 microprocessors, and DSPs.  He funded TOPS Systems Corp. in 1999, and
received the Takeda Techno-Entrepreneurship Award, Tsukuba Venture Award, and ET Award in
hardware in 2001, 2010, and 2011 respectively. Prior to TOPS Systems, he has held several
positions within Texas Instruments and its R&D organization in US and Japan, and within V.M.
Technology, a microprocessor start-up in Japan. He received the Dr. of Information Sciences (the
Ph.D.) degree from the Graduate School of Tohoku University, Sendai, Japan, in 2007, and
participated in the MOT (Management of Technology) program at the Graduate School of
Engineering in Tokyo University from 2004 through 2005. He is also President & CEO of Cool Soft
Corp., and a member of Microprocessor Technical Committee, Multi/Many-core Application
Research Committee, Information System Disruptive Technology Research Committee, and 3D
Semiconductor Sub-Committee of JEITA.